Founding Hardware Engineer

PAX Markets (Headquarters: Menlo Park, CA)

Hardware Engineer FPGA ASIC Verilog SystemVerilog VHDL Silicon Crypto Exchange Fintech HFT Ultra-low latency Digital Design Founding Engineer YC W25 Menlo Park Staff Engineer Robotics

Company: PAX Markets (YC W25)
Location: Menlo Park, CA
Website: https://pax.markets

PAX Markets is building a crypto exchange on a single silicon chip, aiming to be the fastest exchange from crypto to Wall Street. We offer ultra-low latency market access (nanosecond tick-to-trade) for HFT participants via our unique on-chip λ API, and zero-fee trading with cash rebates for all other users. This performance is achieved by implementing exchange logic directly in hardware.

Role: Founding Hardware Engineer
We are seeking an experienced Founding Hardware Engineer to join our early-stage team. As a founding engineer, you will be instrumental in the design, implementation, and verification of the core hardware components of the PAX exchange on silicon/FPGA. You will work on bringing the ultra-low latency vision to reality by architecting and developing the hardware that powers our exchange and the λ API. You'll collaborate closely with software engineers and the founding team.

Responsibilities:
*   Design, implement, and verify hardware components for the exchange using HDLs (Verilog/SystemVerilog/VHDL).
*   Develop and optimize hardware architecture for nanosecond latency performance targeting FPGAs (initially AWS F1 instances) and potentially ASICs.
*   Work on hardware/software co-design and integration, particularly around the λ API.
*   Conduct simulation, synthesis, and timing analysis.
*   Bring-up and debug hardware prototypes.
*   Contribute to system architecture decisions related to hardware implementation.
*   Help establish hardware development methodologies and best practices.

Ideal Candidate:
*   Strong proficiency in hardware description languages (Verilog, SystemVerilog, VHDL).
*   Proven experience in FPGA design, implementation, and verification. ASIC design experience is a plus.
*   Experience with high-speed digital design and low-latency techniques.
*   Familiarity with hardware development tools (simulation, synthesis, P&R).
*   Understanding of computer architecture, network protocols (Ethernet, TCP/IP), and high-performance interconnects.
*   Experience in fintech, HFT, or network processing hardware is highly desirable.
*   Ability to work independently and take ownership in a fast-paced startup environment.
*   Passionate about pushing the boundaries of hardware performance for trading technology.
*   Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.